1. Field of the Invention
The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same.
2. Description of the Related Art
Flash electrically erasable programmable read only memory (EEPROM) is a class of nonvolatile memory devices that are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. Each memory cell is formed on a semiconductor substrate (i.e., a silicon die or chip), having a heavily doped drain region and a source region embedded therein. The source region further contains a lightly doped deeply diffused region and a more heavily doped shallow diffused region embedded into the substrate. A channel region separates the drain region and the source region. The memory cell further includes a multi-layer structure, commonly referred to as a “stacked gate” structure or word line. The multi-layer stacked gate structure typically includes: a thin gate dielectric or tunnel oxide layer formed on the surface of substrate overlying the channel region; a polysilicon floating gate overlying the tunnel oxide; an interpoly dielectric layer overlying the floating gate; and a polysilicon control gate overlying the interpoly dielectric layer. Additional layers, such as a silicide layer (deposited on the control gate), a poly cap layer (deposited on the gate silicide layer), and a silicon oxynitride layer (deposited on the poly cap layer) may be formed over the control gate. A plurality of Flash EEPROM cells may be formed on a single substrate.
The process of forming Flash memory cells is well known and widely practiced throughout the semiconductor industry. After the formation of the memory cells, electrical connections, commonly known as “contacts” and “local interconnect”, must be made to connect the stack gated structures, the source regions and the drain regions to other parts of the chip.
FIG. 1 (Prior Art) shows an exemplary and simplified cross sectional view of a portion of Flash memory cells. The gate structures 210 are formed by a floating gate 214 overlying the gate dielectric layer 212; an interpoly dielectric layer 216 overlying floating gate 214; a control gate 218 overlying interpoly dielectric layer 216; a gate silicide layer 224 deposited on the control gate 218; and a cap layer 228 (of a material such as silicon oxynitride) as a passivating layer deposited on the gate silicide layer 224.
In a conventional process, the source region 202, and the drain region 204 are then formed. The source regions 202 are typically formed by initially affecting a conventional double diffusion implant (DDI). The DDI implants a first dopant (e.g. n-type, such as phosphorous) to form a deeply diffused, but lightly doped N well 202L establishing a graded source-channel junction. The DDI implant is typically driven deeper into the semiconductor substrate 102 by subjecting it to a thermal cycle at high temperature (e.g. 1050° C.). A shallow second implant, commonly referred to as a medium diffused drain (MDD) implant, is then performed (e.g., with arsenic) to create a more heavily doped, but shallower, n+ well 202H embedded within deep N well 202L. The MDD implant also forms the drain region 204.
The sidewall spacers 230 are typically formed of a nitride material using conventional deposition and etching techniques. Alternatively, the sidewall spacers 230 may be formed of an oxide material using chemical vapor deposition (CVD) followed by etching. An etch stop layer 231 is deposited over the semiconductor substrate 102, including over the multi-layer stacked gate structures 210 using conventional techniques, such as CVD. A pre-metal dielectric layer 132 is then deposited over the etch stop layer 231. The pre-metal dielectric layer 132 may include various materials, such as boro-phospho-tetra-ethyl-ortho silicate (BPTEOS) or borophosphosilicate glass (BPSG), formed using plasma enhanced chemical vapor deposition (PECVD).
Self-aligned contacts (SAC) and local interconnects (LI) are made afterwards to connect the stack gated structures, the source regions and the drain regions to other parts of the chip. Self-aligned contacts features are etched with anisotropic pre-metal dielectric (PMD) etch chemistry that does not etch the nitride spacer and etch stop layer. Conventionally, the self-aligned contacts (SAC) and local interconnects (LI) are patterned and filled separately. After pre-metal dielectric layer deposition, a dielectric planarization process, such as CMP, is used to remove dielectric surface topology. Local interconnects (LI) openings 141 are then patterned and etched through the dielectric layer 132, and through the etch stop layer 231 to expose portions of the source regions 202. The openings of LI 141 are formed conventionally with a two-step etch process. A conductive material (or metal) is deposited in the LI openings to form local interconnects. The conductive material, such as tungsten, may be formed using conventional metal deposition techniques, such as CVD and/or physical vapor deposition (PVD). Other conductive materials can be used such as copper. A barrier material (not shown), such as titanium (Ti)/titanium nitride (TiN), is typically deposited to coat the walls of the LI opening prior to the deposition of copper to ensure good adhesion and electrical contact to the walls of the local interconnects 140.
A metal CMP process is used afterwards to remove the excess metal, that is on top of the pre-metal dielectric layer and above the local interconnect feature. After the metal removal, another dielectric layer 133 is deposited. The dielectric layer 133 can include various materials, such as silicon dioxide, BPSG, or low-k dielectric, formed using plasma enhanced chemical vapor deposition (PECVD).
After dielectric layer 133 deposition, openings of contacts 140 are etched through the dielectric layer 133 and dielectric layer 132, and through the etch stop layer 131 to expose portions of the drain regions 204. The openings of contacts 140 are formed conventionally with a multi-step etch process. A conductive material, such as tungsten, may be formed using conventional metal deposition techniques, such as CVD and/or physical vapor deposition (PVD). Other conductive materials can be used such as copper. A barrier material (not shown), such as titanium (Ti)/titanium nitride (TiN), is typically deposited to coat the walls of the LI opening prior to the deposition of copper to ensure good adhesion and electrical contact to the walls of the contacts 140.
To prevent shorting of contacts 140 with local interconnects 141, a minimum distance, Dmin, between contacts 140 and local interconnects 141 is required. This minimum distance requirement limits the miniaturization of memory cells.
FIG. 2 (Prior Art) is a top view of FIG. 1. FIG. 1 is a cross sectional view along line A-A of FIG. 2. A memory cell 10 includes a gate structure 210, a source region 202, and a drain region 204, which is below the self-aligned contact 140. Control gate 218 runs across the memory cells. Self-aligned contacts 140 and local interconnects 141, which runs across the memory cells, are allowed to cover part of the gate structure 210, but a minimum distance, Dmin, is needed to ensure no shorting between the contacts 140 and the local interconnects 141. This requirement of minimum distance, Dmin, makes patterning contacts and local interconnects difficult. Especially, when the contacts 140 are patterned after the local interconnects 141. Accurate masks alignment and wide spacing between the contacts 140 and local interconnects 141 must be used to ensure that contacts 140 do not short local interconnects 141. The required wide spacing significantly increases semiconductor memory core cell size and therefore adversely impacts semiconductor device and memory densities. Moreover, this problem is becoming more critical as separation between adjacent gate structures diminishes with semiconductor technology feature size scaling down to sub-quarter micron level and below.
In view of the foregoing, there is a need for an improved processing method that allows further miniaturization of memory devices without adversely affecting device performance.